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ORCIDMotohiro Enkaku
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1990 – 1999
- 1998
[j2]Tomoaki Yabe, Shinji Miyano, Katsuhiko Sato, Masaharu Wada, Ryo Haga, Osamu Wada, Motohiro Enkaku, Takehiko Hojyo, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Kenji Numata:
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. IEEE J. Solid State Circuits 33(11): 1752-1757 (1998)- [c1]Hideki Takeuchi, Tomoaki Yabe, Shinji Miyano, Takehiko Hojo, Motohiro Enkaku, Masaaki Yamada, Masami Murakata:
A DRAM module generator with an expandable cell array scheme. CICC 1998: 287-290 - 1995
- [j1]Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea:
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM. IEEE J. Solid State Circuits 30(11): 1281-1285 (1995)
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