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ORCIDDmitry G. Netis
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2000 – 2009
- 2000
[j2]Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman:
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. IEEE J. Solid State Circuits 35(5): 713-718 (2000)
1990 – 1999
- 1999
- [j1]Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman:
A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. IEEE J. Solid State Circuits 34(11): 1580-1588 (1999)
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last updated on 2024-04-24 23:19 CEST by the dblp team
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