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ORCIDZihan Wu 0006
Person information
- affiliation: Tsinghua University, School of Integrated Circuits, Beijing, China
Other persons with the same name
- Zihan Wu — disambiguation page
- Zihan Wu 0001
![[0000-0001-6342-9881]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-6342-9881")
— Xiamen University, China - Zihan Wu 0002 — University of Michigan-Ann Arbor, School of Information, MI, USA (and 1 more)
- Zihan Wu 0003 — Jiangsu University, Zhenjiang, China
- Zihan Wu 0004 — China Agricultural University, Beijing, China
- Zihan Wu 0005 — Fudan University, State Key Laboratory of ASIC & System, Shanghai, China
- Zihan Wu 0007 — Shanghai Rongyue Private Entry-Exit Services Co., Ltd, China
- Zihan Wu 0008 — Hebei University, School of Cyber Security and Computer, Baoding, China
- Zihan Wu 0009 — EPFL, Lausanne, Switzerland
- Zihan Wu 0010 — Harbin Institute of Technology, School of Electronics and Information Engineering / School of Information Science and Engineering, China
- Zihan Wu 0011 — Shenyang University of Technology, College of Information Science and Engineering, China
- Zihan Wu 0012 — Zhejiang University, School of Mechanical Engineering, Hangzhou, China
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2020 – today
- 2024
[j3]Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. IEEE J. Solid State Circuits 59(1): 90-101 (2024)- [c5]Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin:
ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j2]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits 58(1): 243-255 (2023) - [j1]Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. IEEE J. Solid State Circuits 58(6): 1798-1809 (2023) - [c4]Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. ISSCC 2023: 248-249 - [c3]Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin:
TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. ISSCC 2023: 254-255 - 2022
- [c2]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC 2022: 1-3 - [c1]Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. ISSCC 2022: 466-468
Coauthor Index
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