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ORCIDTaiga Takata
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2010 – 2019
- 2013
[j5]Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga:
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6: 127-134 (2013)- 2012
- [j4]Taiga Takata, Yusuke Matsunaga:
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5: 55-62 (2012) - 2011
- [c7]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - [c6]Taiga Takata, Yusuke Matsunaga:
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS 2011: 246-251 - 2010
- [c5]Taiga Takata, Yusuke Matsunaga:
A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA 2010: 289
2000 – 2009
- 2009
- [j3]Taiga Takata, Yusuke Matsunaga:
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3268-3275 (2009) - [j2]Taiga Takata, Yusuke Matsunaga:
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. 2: 200-211 (2009) - [c4]Taiga Takata, Yusuke Matsunaga:
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356 - 2008
- [c3]Taiga Takata, Yusuke Matsunaga:
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC 2008: 144-147 - 2006
- [j1]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. 89-C(3): 377-383 (2006) - [c2]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006 - 2005
- [c1]Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC 2005: 137-140
Coauthor Index
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