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ORCIDRainer Schlör
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2010 – 2019
- 2018
[c7]Rainer Schlör, Jürgen Jung:
Analysis Using the Business Support Matrix: Elaborating Potential for Improving Application Landscapes in Logistics. EDOC Workshops 2018: 192-199
2000 – 2009
- 2006
- [c6]Jan Staschulat, Jörn-Christian Braam, Rolf Ernst, Thomas Rambow, Rainer Schlör, Rainer Busch:
Cost-Efficient Worst-Case Execution Time Analysis in Industrial Practice. ISoLA 2006: 204-211 - 2002
- [b1]Rainer Schlör:
Symbolic timing diagrams: a visual formalism for model verification. University of Oldenburg, Germany, 2002, pp. 1-248
1990 – 1999
- 1998
- [c5]Rainer Schlör, Bernhard Josko, Dieter Werth:
Using a Visual Formalism for Design Verification in Industrial Environments. Services and Visualization: Towards User-Friendly Design 1998: 208-221 - 1996
- [c4]Konrad Feyerabend, Rainer Schlör:
Hardware synthesis from requirement specifications. EURO-DAC 1996: 496-501 - 1995
- [c3]Rainer Schlör, Franz Korf:
Verification of a production cell controller using symbolic timing diagrams. EURO-DAC 1995: 548-553 - [p3]Werner Damm, Hardi Hungar, Peter Kelb, Rainer Schlör:
Statecharts. Formal Development of Reactive Systems 1995: 131-149 - [p2]Franz Korf, Rainer Schlör:
Symbolic Timing Diagrams. Formal Development of Reactive Systems 1995: 311-331 - 1994
- [c2]Franz Korf, Rainer Schlör:
Interface Controller Synthesis from Requirement Specifications. EDAC-ETC-EUROASIC 1994: 385-394 - 1993
- [j1]Johannes Helbig, Rainer Schlör, Werner Damm, Gert Döhmen, Peter Kelb:
VHDL/S - integrating statecharts, timing diagrams, and VHDL. Microprocess. Microprogramming 38(1-5): 571-580 (1993) - [c1]Werner Damm, Bernhard Josko, Rainer Schlör:
A net-based semantics for VHDL. EURO-DAC 1993: 514-519 - [p1]Werner Damm, Bernhard Josko, Rainer Schlör:
Specification and verification of VHDL-based system-level hardware designs. Specification and validation methods 1993: 331-409
Coauthor Index
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