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Chenglong Liang
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2020 – today
- 2024
- [j2]Ya Zhao, Chao Fan, Yuanxing Peng, Chenglong Liang, Jun Yin, Pui-In Mak, Li Geng:
A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2604-2608 (2024) - [j1]Bingjun Tang, Yuanrui Li, Chenglong Liang, Zhongming Xue, Zhuoqi Guo, Li Geng:
Design of CMOS Integrated Circulator Based on Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4476-4480 (2024) - 2022
- [c3]Lingyun Liu, Chenglong Liang, Zhuoqi Guo, Zhongming Xue, Li Geng:
A Cap-Less High PSR and Low Output Noise Low-Dropout Regulator for Cryogenic Applications. ICTA 2022: 148-149 - 2021
- [c2]Yi Xie, Chenglong Liang, Bingjun Tang, Lingyun Liu, Li Geng:
A 47K Noise Temperature CMOS S-band LNA for Cryogenic Applications. ICTA 2021: 179-180 - [c1]Shengyu Liang, Youze Xin, Chenglong Liang, Bin Zhang, Yanlong Zhang, Xiaoli Wang, Li Geng:
A 0.025% DC Current Mismatch Charge Pump for PLL Applications. MWSCAS 2021: 700-703
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last updated on 2025-01-09 12:53 CET by the dblp team
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