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ORCIDStefanos Sidiropoulos
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Journal Articles
- 2013
[j8]Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos:
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. IEEE J. Solid State Circuits 48(12): 3038-3048 (2013)- 2003
- [j7]Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos:
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits 38(5): 747-754 (2003) - 2000
- [j6]Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz:
A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE J. Solid State Circuits 35(11): 1600-1610 (2000) - 1998
- [j5]Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos:
High-speed electrical signaling: overview and limitations. IEEE Micro 18(1): 12-24 (1998) - 1997
- [j4]Stefanos Sidiropoulos, Mark Horowitz:
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. IEEE J. Solid State Circuits 32(5): 681-690 (1997) - [j3]Stefanos Sidiropoulos, Mark A. Horowitz:
A semidigital dual delay-locked loop. IEEE J. Solid State Circuits 32(11): 1683-1692 (1997) - 1996
- [j2]Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon:
A speed, power, and supply noise evaluation of ECL driver circuits. IEEE J. Solid State Circuits 31(1): 38-45 (1996) - 1991
- [j1]Manolis Katevenis, Stefanos Sidiropoulos, Costas Courcoubetis:
Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. IEEE J. Sel. Areas Commun. 9(8): 1265-1279 (1991)
Conference and Workshop Papers
- 2022
- [c5]Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang
, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos:
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. VLSI Technology and Circuits 2022: 26-27 - 2013
- [c4]Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos:
A 10.3GS/s 6b flash ADC for 10G Ethernet applications. ISSCC 2013: 462-463 - 2006
- [c3]Shahriar Rabii, Nikhil Acharya, Pak Chau, Joseph Dao, Arnold Feldman, Haw-Jyh Liaw, Dean Liu, Marc Loinaz, Manuel Luschas, Azmeer Salleh, Siddharth Sheth, Stefanos Sidiropoulos, Donald Stark, Shwetabh Verma:
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. ISSCC 2006: 930-939 - [c2]Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz:
Improving CDR Performance via Estimation. ISSCC 2006: 1296-1303 - 2003
- [c1]Dean Liu, Stefanos Sidiropoulos, Mark Horowitz:
A Framework for Designing Reusable Analog Circuits. ICCAD 2003: 375-381
Coauthor Index
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