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2020 – today
- 2024
[b1]Adrian Kneip:
Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification. Catholic University of Louvain, Louvain-la-Neuve, Belgium, 2024- [i1]Yufeng Yang, Adrian Kneip, Charlotte Frenkel:
EvGNN: An Event-driven Graph Neural Network Accelerator for Edge Vision. CoRR abs/2404.19489 (2024) - 2023
- [j3]Adrian Kneip
, Martin Lefebvre, Julien Verecken, David Bol:
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization. IEEE J. Solid State Circuits 58(7): 1871-1884 (2023) - [j2]Adrian Kneip, David Bol:
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1311-1323 (2023) - 2022
- [c2]Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol:
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization. ESSCIRC 2022: 157-160 - 2021
- [j1]Adrian Kneip, David Bol:
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1931-1944 (2021) - [c1]Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol:
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits 2021: 1-2
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