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Conference and Workshop Papers
- 2016
[c6]Bonita Bhaskaran, Amit Sanghani, Kaushik Narayanun, Ayub Abdollahian, Amit Laknaur:
Test method and scheme for low-power validation in modern SOC integrated circuits. VTS 2016: 1-6- [c5]Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn
:
Flexible scan interface architecture for complex SoCs. VTS 2016: 1-6 - [c4]Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha:
Dynamic docking architecture for concurrent testing and peak power reduction. VTS 2016: 1-6 - [c3]Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani:
A programmable method for low-power scan shift in SoC integrated circuits. VTS 2016: 1-6 - 2011
- [c2]Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu:
A clock-gating based capture power droop reduction methodology for at-speed scan testing. DATE 2011: 197-203 - [c1]Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu:
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. VTS 2011: 219-224
Coauthor Index
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