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ORCIDHyein Lee 0001
Person information
- affiliation: University of California at San Diego, La Jolla, California, USA
Other persons with the same name
- Hyein Lee 0002 — Korea Advanced Institute of Science and Technology, Daejeon, Korea
- Hyein Lee 0003 — Samsung Electronics, Gyeonggi-Do, Korea
- Hyein Lee 0004 — Yonsei University, Seoul, Korea
- Hyein Lee 0005 — National Cancer Center, Goyang, Korea
- Hyein Lee 0006
![[0000-0002-1368-8874]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-1368-8874")
— Jeonbuk National University, Jeonju, Korea - Hyein Lee 0007 — Inje University, South Korea
- Hyein Lee 0008 — Samsung Electronics, Memory Business Division, Hwaseong, South Korea
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Books and Theses
- 2018
[b1]Hyein Lee:
Physical Design and Technology Optimizations for Advanced VLSI Manufacturing. University of California, San Diego, USA, 2018
Journal Articles
- 2020
- [j4]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez:
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2860-2871 (2020) - 2019
- [j3]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez:
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66: 96-111 (2019) - 2018
- [j2]Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li:
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1459-1472 (2018) - 2017
- [j1]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1075-1088 (2017)
Conference and Workshop Papers
- 2017
- [c12]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC 2017: 51:1-51:6 - [c11]Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu:
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD 2017: 667-674 - [c10]Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang:
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED 2017: 104-110 - 2016
- [c9]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Measuring progress and value of IC implementation technology. ICCAD 2016: 27 - 2015
- [c8]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC 2015: 68:1-68:6 - [c7]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD 2015: 867-873 - 2014
- [c6]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI 2014: 27-32 - [c5]Andrew B. Kahng, Hyein Lee:
Minimum implant area-aware gate sizing and placement. ACM Great Lakes Symposium on VLSI 2014: 57-62 - [c4]Andrew B. Kahng, Hyein Lee:
Timing margin recovery with flexible flip-flop timing model. ISQED 2014: 496-503 - 2013
- [c3]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee:
Smart non-default routing for clock power reduction. DAC 2013: 91:1-91:7 - [c2]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar:
High-performance gate sizing with a signoff timer. ICCAD 2013: 450-457 - [c1]Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani:
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP 2013: 1-8
Coauthor Index
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