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2020 – today
- 2023
[j1]Chi-Hsiang Huang
, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. IEEE J. Solid State Circuits 58(1): 68-77 (2023)- 2022
- [c5]Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C. Rudell:
A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. ESSCIRC 2022: 493-496 - [c4]Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe:
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. ISSCC 2022: 1-3 - [c3]Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. ISSCC 2022: 222-224 - 2020
- [c2]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits 2020: 1-2 - [c1]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits 2020: 1-2
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