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2020 – today
- 2024
[i2]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics. CoRR abs/2404.04132 (2024)- 2023
- [j4]Sören Tempel
, Vladimir Herdt, Rolf Drechsler:
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. 10(11): 9544-9555 (2023) - [c10]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. FDL 2023: 1-8 - [c9]Sören Tempel, Tobias Brandt, Christoph Lüth:
Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture. TFP 2023: 16-35 - [d3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. Zenodo, 2023
- 2022
- [j3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. 14(4): 195-198 (2022) - [j2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126: 102456 (2022) - [c8]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC 2022: 160-165 - [c7]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA 2022: 77-82 - [c6]Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler:
3D Visualization of Symbolic Execution Traces. FDL 2022: 1-8 - [d2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. Zenodo, 2022 - 2021
- [j1]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116: 102135 (2021) - [c5]Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler:
Mutation-based Compliance Testing for RISC-V. ASP-DAC 2021: 55-60 - [c4]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC 2021: 667-672 - [c3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE 2021: 218-221 - [c2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL 2021: 1-7 - [d1]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. Zenodo, 2021 - 2020
- [c1]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD 2020: 312-315 - [i1]Sören Tempel, Tristan Bruns:
RIOT-POLICE: An implementation of spatial memory safety for the RIOT operating system. CoRR abs/2005.09516 (2020)
Coauthor Index
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