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2020 – today
- 2023
[c10]Jonathan Fontaine, Mohamed Benazouz, Lilia Zaourar, Roselyne Chotin:
Improving Integrated Circuit Security Using Mathematical Model Based on Clique Covering Reformulation. CoDIT 2023: 1717-1722- 2022
- [c9]Ilias Bournias, Roselyne Chotin, Lionel Lacassagne:
Using HLS for Designing a Parametric Optical Flow Hierarchical Algorithm in FPGAs. ISCAS 2022: 1600-1604 - [c8]Daniela Genius, Roselyne Chotin:
Model to Hardware: System-level Modeling for Wearable Devices. MODELSWARD 2022: 387-394 - 2021
- [c7]Gabriel Rocherolle, Roselyne Chotin:
Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits. DTIS 2021: 1-4 - [c6]Ilias Bournias, Roselyne Chotin, Lionel Lacassagne:
FPGA Acceleration of the Horn and Schunck Hierarchical Algorithm. ISCAS 2021: 1-5 - 2020
- [c5]François Pêcheux, Liliana Andrade, Marie-Minerve Louërat, Ilias Bournias, Roselyne Chotin, Daniela Genius:
Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions. FDL 2020: 1-8 - [c4]Daniela Genius, Ilias Bournias, Ludovic Apvrille, Roselyne Chotin:
Model-Based Virtual Prototyping of CPS: Application to Bio-Medical Devices. MODELSWARD (Revised Selected Papers) 2020: 74-96 - [c3]Daniela Genius, Ilias Bournias, Ludovic Apvrille, Roselyne Chotin:
High-level Partitioning and Design Space Exploration for Cyber Physical Systems. MODELSWARD 2020: 84-91 - [c2]Joël Cathébras, Roselyne Chotin
:
A HDL Generator for Flexible and Efficient Finite-Field Multipliers on FPGAs. WAIFI 2020: 75-91
2000 – 2009
- 2002
- [c1]Roselyne Chotin, Habib Mehrez:
A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard. ICECS 2002: 603-606
Coauthor Index
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