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Santosh Yachareni

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2020 – today

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2021
[c6]
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  dblp key:
  - conf/dft/GhoshalSYZKP21
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  - https://dblp.org/rec/conf/dft/GhoshalSYZKP21
Nabanita Ghoshal, Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati:
Mitigation of the impact of across chip systematic process variation using a novel system level design. DFT 2021: 1-4
[c5]
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  - conf/iolts/SaraswatulaYZPC21
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Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Kumar Pulipati, Joy Chen, Teja Masina:
Robust Adaptive Read Scheme for 7nm Configuration SRAMs. IOLTS 2021: 1-4
[c4]
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  - conf/isncc/GunasekaranRY21
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Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni:
Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. ISNCC 2021: 1-5
[c3]
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  - conf/isncc/KothaRAYK21
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Suresh Babu Kotha, Kumar Rahul, Mohammad Anees, Santosh Yachareni, Subodh Kumar:
High speed low power SEU tolerant Pseudo dual port memory in 7nm. ISNCC 2021: 1-5
2020
[c2]
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  - conf/icccs/RahulY20
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Kumar Rahul, Santosh Yachareni:
Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications. ICCCS 2020: 1-5
[c1]
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  - conf/iccel/RahulY20
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Kumar Rahul, Santosh Yachareni:
Area and power efficient ECC for multiple adjacent bit errors in SRAMs. ICCE 2020: 1-4

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