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Qingsheng Hu
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2020 – today
- 2022
- [j6]Yan Wang, Qingsheng Hu:
A COM Based High Speed Serial Link Optimization Using Machine Learning. IEICE Trans. Electron. 105-C(11): 684-691 (2022) - [c13]Julaiti Abulizi, Qingsheng Hu, Wei Wang:
Delay Optimization of Power Internet of Things based on Edge-Cloud Collaboration. ICCT 2022: 905-910 - [c12]Julaiti Abulizi, Qingsheng Hu, Wang Wei:
Quantum Cryptography Technology and Application in Smart Grid. ICCT 2022: 1213-1217 - 2020
- [j5]Yongzheng Zhan, Qingsheng Hu, Yinhang Zhang:
DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane. IEICE Trans. Electron. 103-C(2): 48-58 (2020)
2010 – 2019
- 2019
- [c11]Qingsheng Hu, Xiangning Fan, Qiaowei Zhang:
An Effective Differential Power Attack Method for Advanced Encryption Standard. CyberC 2019: 58-61 - 2018
- [j4]Yinhang Zhang, Qingsheng Hu:
A 33 Gb/s combined adaptive CTLE and half-rate look-ahead DFE in 0.13 µm BiCMOS technology for serial link. IEICE Electron. Express 15(4): 20170764 (2018) - [c10]Weifeng Fu, Qingsheng Hu, Rong Wang:
A 40 Gb/s PAM4 SerDes Receiver in 65nm CMOS Technology. CCECE 2018: 1-4 - [c9]Xiao Zheng, Qingsheng Hu, Jun Feng:
Two Improved Algorithms for Layered QC-LDPC Decoding Algorithm. CCECE 2018: 1-4 - 2017
- [c8]Yongzheng Zhan, Qingsheng Hu, Yinhang Zhang:
IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link. WWIC 2017: 271-281 - [c7]Yinhang Zhang, Qingsheng Hu, Yongzheng Zhan:
A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology. WWIC 2017: 292-303 - 2015
- [j3]Qingsheng Hu, Xiujuan Lei:
PPI网络的改进马尔科夫聚类算法 (Improved MCL Clustering Algorithm in PPI Networks). 计算机科学 42(7): 108-113 (2015) - 2014
- [c6]Yongsheng He, Qingsheng Hu, Jun Feng:
A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration. CSNDSP 2014: 203-207 - 2012
- [c5]Tangbiao Zhang, Qingsheng Hu:
A high-speed and low-power up/down counter in 0.18-μm CMOS technology. WCSP 2012: 1-3 - 2011
- [c4]Feng Zhou, Qingsheng Hu:
High-performance FPGA implementation of packet reordering for multiple TCP connections. ISCIT 2011: 318-322 - 2010
- [j2]Qingsheng Hu, Hua-An Zhao:
Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm. IEICE Trans. Electron. 93-C(3): 279-287 (2010)
2000 – 2009
- 2008
- [c3]Qingsheng Hu, Hua-An Zhao, Chen Liu:
A Programmable Frequency Divider in 0.18µm CMOS Library. ISVLSI 2008: 157-161 - 2005
- [c2]Qingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao:
Low complexity parallel Chien search architecture for RS decoder. ISCAS (1) 2005: 340-343 - 2003
- [c1]Jing Liu, Mounir Hamdi, Qingsheng Hu:
Stable and Practical Scheduling Algorithms for High Speed Virtual Output Queuing Switches. ISCC 2003: 515-520
1990 – 1999
- 1999
- [j1]Qingsheng Hu, Xiaoyan Wang, Zhenquan Zhuang:
A distributed algorithm for multi-region problem in BEM. J. Comput. Sci. Technol. 14(6): 558-564 (1999)
Coauthor Index
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