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Journal Articles
- 2023
[j3]Aurélien Alacchi
, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon:
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2028-2036 (2023)- [j2]Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon:
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1204-1213 (2023) - 2022
- [j1]Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel:
Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution. ACM J. Emerg. Technol. Comput. Syst. 18(2): 40:1-40:26 (2022)
Conference and Workshop Papers
- 2024
- [c7]Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon:
Secure eFPGA Configuration: A System-Level Approach. ARC 2024: 151-165 - 2022
- [c6]Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. ISCAS 2022: 273-277 - [c5]Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon:
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. VLSI-SoC 2022: 1-6 - 2021
- [c4]Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. DATE 2021: 1-6 - 2020
- [c3]Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud:
Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE 2020: 1187-1192 - [c2]Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles:
Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. ISLPED 2020: 121-126 - 2019
- [c1]Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles:
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. VLSI-SoC 2019: 166-171
Coauthor Index
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