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2020 – today
- 2022
[c5]Tommaso Zanotti, Paolo Pavan
, Francesco Maria Puglisi:
Self-consistent Automated Parameter Extraction of RRAM Physics-Based Compact Model. ESSDERC 2022: 316-319- [i1]Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza:
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR abs/2205.09388 (2022) - 2021
- [j2]Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan:
Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4433-4443 (2021) - [c4]Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan:
Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories. IRPS 2021: 1-6 - 2020
- [j1]Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan:
Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(4): 478-487 (2020) - [c3]Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan:
Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations. AICAS 2020: 31-35 - [c2]Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan:
Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise. IRPS 2020: 1-5
2010 – 2019
- 2019
- [c1]Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan:
SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model. ESSDERC 2019: 130-133
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