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2020 – today
- 2021
[j10]Apisit Rattanatranurak, Surin Kittitornkun
:
Optimizing MultiStack Parallel (MSP) Sorting Algorithm. J. Mobile Multimedia 17(4): 723-748 (2021)- 2020
- [j9]Apisit Rattanatranurak, Surin Kittitornkun:
A MultiStack Parallel (MSP) Partition Algorithm Applied to Sorting. J. Mobile Multimedia 16(3): 293-316 (2020)
2010 – 2019
- 2017
- [j8]Khamphao Sisaat, Surin Kittitornkun, Hiroaki Kikuchi, Chaxiong Yukonhiatou, Masato Terada, Hiroshi Ishii:
A Spatio-Temporal malware and country clustering algorithm: 2012 IIJ MITF case study. Int. J. Inf. Sec. 16(5): 459-473 (2017) - 2016
- [j7]Ratthaslip Ranokphanuwat, Surin Kittitornkun:
Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUs. J. Supercomput. 72(3): 1063-1091 (2016) - 2013
- [j6]Khamphao Sisaat, Hiroaki Kikuchi, Shunji Matsuo, Masato Terada, Masashi Fujiwara, Surin Kittitornkun:
Time Zone Correlation Analysis of Malware/Bot Downloads. IEICE Trans. Commun. 96-B(7): 1753-1763 (2013) - 2012
- [c10]N. Hiroguchi, Hiroaki Kikuchi, Khamphao Sisaat, Surin Kittitornkun:
Geographical Visualization of Malware Download for Anomaly Detection. AsiaJCIS 2012: 74-78 - 2010
- [c9]Thinh Ngoc Tran, Surin Kittitornkun:
Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPS. DELTA 2010: 217-221
2000 – 2009
- 2009
- [j5]Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama:
PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPS. IEICE Trans. Inf. Syst. 92-D(5): 1049-1061 (2009) - 2007
- [c8]Thinh Ngoc Tran, Surin Kittitornkun:
FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS. APNOMS 2007: 334-343 - [c7]Tran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama:
Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPS. FPT 2007: 121-128 - 2006
- [c6]Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama:
Manifold similarity search of DNA sequences with reconfigurable hardware. FPGA 2006: 231 - [c5]Kridsadakorn Chaichoompu, Surin Kittitornkun, Sissades Tongsima:
MT-ClustalW: multithreading multiple sequence alignment. IPDPS 2006 - 2003
- [j4]Surin Kittitornkun, Yu Hen Hu:
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops. J. Supercomput. 24(3): 229-249 (2003) - [j3]Surin Kittitornkun, Yu Hen Hu:
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 208-217 (2003) - [c4]Surin Kittitornkun, Yu Hen Hu:
Supersystolic arrays on large-scale FPGA structures. ISCAS (2) 2003: 756-759 - 2001
- [j2]Surin Kittitornkun, Yu Hen Hu:
Efficient Implementation of Nested-Loop Multimedia Algorithms. EURASIP J. Adv. Signal Process. 2001(3): 129-146 (2001) - [j1]Surin Kittitornkun, Yu Hen Hu:
Frame-level pipelined motion estimation array processor. IEEE Trans. Circuits Syst. Video Technol. 11(2): 248-251 (2001) - [c3]Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull:
Low bit rate video sequence coding artifact removal. MMSP 2001: 53-58 - 2000
- [c2]Adam H. Li, Surin Kittitornkun, Yu Hen Hu, Dong-Seek Park, John D. Villasenor:
Data Partitioning and Reversible Variable Length Codes for Robust Video Communications. Data Compression Conference 2000: 460-469 - [c1]Seungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull:
Blocking Artifact Free Inverse Discrete Cosine Transform. ICIP 2000: 869-872
Coauthor Index
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