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Jinchen Wang
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2020 – today
- 2024
- [c3]Jinchen Wang, Isaac B. Harris, Xibi Chen, Dirk R. Englund, Ruonan Han:
A CMOS-Integrated Color Center Pulse-Sequence Control and Detection System. CICC 2024: 1-2 - 2023
- [j6]Yi Xiong, Wenjie Zhai, Xueyong Xu, Jinchen Wang, Zongwei Zhu, Cheng Ji, Jing Cao:
Ability-aware knowledge distillation for resource-constrained embedded devices. J. Syst. Archit. 141: 102912 (2023) - [c2]Jinchen Wang, Mohamed I. Ibrahim, Isaac B. Harris, Nathan M. Monroe, Muhammad Ibrahim Wasiq Khan, Xiang Yi, Dirk R. Englund, Ruonan Han:
THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data Interface. ISSCC 2023: 504-505 - 2021
- [j5]Xiang Yi, Cheng Wang, Xibi Chen, Jinchen Wang, Jesús Grajal, Ruonan Han:
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture. IEEE J. Solid State Circuits 56(2): 327-339 (2021) - [j4]Xiang Yi, Jinchen Wang, Marco Colangelo, Cheng Wang, Kenneth E. Kolodziej, Ruonan Han:
Realization of In-Band Full-Duplex Operation at 300 and 4.2 K Using Bilateral Single-Sideband Frequency Conversion. IEEE J. Solid State Circuits 56(5): 1387-1397 (2021) - 2020
- [j3]Chuan Li, Fei You, Jun Peng, Jinchen Wang, Muhammad Furqan Haider, Songbai He:
Co-Design of Matching Sub-Networks to Realize Broadband Symmetrical Doherty With Configurable Back-Off Region. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1730-1734 (2020) - [j2]Weiming Shi, Songbai He, Jun Peng, Jinchen Wang:
Digital Dual-Input Doherty Configuration for Ultrawideband Application. IEEE Trans. Ind. Electron. 67(9): 7509-7518 (2020) - [c1]Xiang Yi, Cheng Wang, Muting Lu, Jinchen Wang, Jesús Grajal, Ruonan Han:
4.8 A Terahertz FMCW Comb Radar in 65nm CMOS with 100GHz Bandwidth. ISSCC 2020: 90-92
2010 – 2019
- 2019
- [j1]Chuan Li, Fei You, Songbai He, Xiaobin Tang, Weiming Shi, Jinchen Wang:
High-Efficiency Power Amplifier Employing Minimum-Power Harmonic Active Load Modulator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(8): 1371-1375 (2019)
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last updated on 2024-08-05 21:13 CEST by the dblp team
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