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ORCIDRaviteja Theertham
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2020 – today
- 2024
[j6]Sharvil Patil
, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury:
A -90-dBFS-IM3, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors. IEEE J. Solid State Circuits 59(12): 4225-4236 (2024)- [c5]Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury:
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC 2024: 390-392 - 2023
- [c4]Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat:
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. CICC 2023: 1-2 - 2022
- [j5]Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan:
Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. IEEE J. Solid State Circuits 57(11): 3418-3428 (2022) - [j4]Raviteja Theertham, Shanthi Pavan:
Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 1991-1995 (2022) - [c3]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - 2020
- [j3]Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan:
Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. IEEE J. Solid State Circuits 55(9): 2429-2442 (2020) - [c2]Raviteja Theertham, Shanthi Pavan:
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. ISCAS 2020: 1
2010 – 2019
- 2019
- [j2]Raviteja Theertham, Shanthi Pavan:
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2831-2842 (2019) - [j1]Shanthi Pavan, Raviteja Theertham:
Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1618-1622 (2019) - [c1]Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan:
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. VLSI Circuits 2019: 226-
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