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Bonan Zhang
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2020 – today
- 2024
- [j2]Peter Deaville, Bonan Zhang, Naveen Verma:
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection. IEEE J. Solid State Circuits 59(7): 2070-2080 (2024) - [c10]Bonan Zhang, Chia-Yu Chen, Naveen Verma:
Reshape and Adapt for Output Quantization (RAOQ): Quantization-aware Training for In-memory Computing Systems. ICML 2024 - [c9]Bonan Zhang, Chao Chen, Ickjai Lee, Kyungmi Lee, Kok-Leong Ong:
Clustering-based Evaluation Framework of Feature Extraction Approaches for ECG Biometric Authentication. IJCNN 2024: 1-9 - 2023
- [c8]Peter Deaville, Bonan Zhang, Naveen Verma:
A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up. ESSCIRC 2023: 21-24 - [c7]Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag:
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. ESSCIRC 2023: 25-28 - 2022
- [c6]Bonan Zhang, Peter Deaville, Naveen Verma:
Statistical computing framework and demonstration for in-memory computing systems. DAC 2022: 979-984 - [c5]Peter Deaville, Bonan Zhang, Naveen Verma:
A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout. VLSI Technology and Circuits 2022: 268-269 - 2021
- [j1]Bonan Zhang, Lung-Yen Chen, Naveen Verma:
Neural Network Training With Stochastic Hardware Models and Software Abstractions. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1532-1542 (2021) - [c4]Bonan Zhang, Jingjin Li, Chao Chen, Kyungmi Lee, Ickjai Lee:
A Practical Botnet Traffic Detection System Using GNN. CSS 2021: 66-78 - [c3]Peter Deaville, Bonan Zhang, Lung-Yen Chen, Naveen Verma:
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area. ESSCIRC 2021: 75-78 - [c2]Peter Deaville, Bonan Zhang, Lung-Yen Chen, Naveen Verma:
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area. ESSDERC 2021: 75-78
2010 – 2019
- 2019
- [c1]Bonan Zhang, Lung-Yen Chen, Naveen Verma:
Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations. ICASSP 2019: 1388-1392
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