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2020 – today
- 2024
[j1]Fatemeh Serajeh-hassani
, Mohammad Sadrosadati, Nezam Rohbani, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad:
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes. ACM Trans. Design Autom. Electr. Syst. 29(3): 42:1-42:18 (2024)- 2021
- [c7]Sebastian Pointner, Sven Wenzek, Robert Wille:
SMT-Based Placement for System-on-Chip Design. ISCAS 2021: 1-5 - 2020
- [c6]Sebastian Pointner, Pablo González de Aledo, Robert Wille:
YASSi: Yet Another Symbolic Simulator Large (Tool Demo). DEXA Workshops 2020: 25-31
2010 – 2019
- 2019
- [c5]Sebastian Pointner, Pablo González de Aledo, Robert Wille:
Generic Error Localization for the Electronic System Level. DDECS 2019: 1-4 - [c4]Sebastian Pointner, Andreas Grimmer, Robert Wille:
Exact Stimuli Minimization for Simulation-Based Verification. ISCAS 2019: 1-5 - [c3]Sebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille:
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows. ISVLSI 2019: 241-246 - [c2]Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad:
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes. ISVLSI 2019: 615-620 - [c1]Sebastian Pointner, Robert Wille:
Did We Test Enough? Functional Coverage for Post-Silicon Validation. ITC-Asia 2019: 31-36
Coauthor Index
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