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ORCIDM. Enamul Amyeen
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
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Journal Articles
- 2021
[j6]Irith Pomeranz
, M. Enamul Amyeen:
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1711-1720 (2021)- [j5]Irith Pomeranz, M. Enamul Amyeen:
Logic Diagnosis with Hybrid Fail Data. ACM Trans. Design Autom. Electr. Syst. 26(3): 19:1-19:13 (2021) - 2017
- [j4]Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Test Modification for Reduced Volumes of Fail Data. ACM Trans. Design Autom. Electr. Syst. 22(4): 67:1-67:17 (2017) - [j3]Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1497-1505 (2017) - 2016
- [j2]Shraddha Bodhe, M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
Diagnostic Fail Data Minimization Using an N-Cover Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1198-1202 (2016) - 2003
- [j1]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 922-936 (2003)
Conference and Workshop Papers
- 2024
- [c26]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Generating Storage-Aware Test Sets Targeting Several Fault Models. ISVLSI 2024: 15-20 - 2022
- [c25]Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman:
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults. ATS 2022: 120-125 - 2018
- [c24]Naixing Wang, Irith Pomeranz, Brady Benware, M. Enamul Amyeen, Srikanth Venkataraman:
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. DFT 2018: 1-6 - 2017
- [c23]Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen:
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure. ITC 2017: 1-9 - 2016
- [c22]M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman:
A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction. ATS 2016: 138-143 - [c21]M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma:
A novel diagnostic test generation methodology and its application in production failure isolation. ITC 2016: 1-10 - [c20]Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen:
Diagnostic resolution improvement through learning-guided physical failure analysis. ITC 2016: 1-10 - [c19]Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman:
Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm. VTS 2016: 1-6 - 2015
- [c18]M. Enamul Amyeen:
Innovative practices session 5C: Advancements in test -keeping moore moving! VTS 2015: 1 - 2014
- [c17]Bo Yao, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen:
Built-in generation of functional broadside tests considering primary input constraints. ACM Great Lakes Symposium on VLSI 2014: 237-238 - 2011
- [c16]M. Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan:
Logic BIST silicon debug and volume diagnosis methodology. ITC 2011: 1-10 - 2010
- [c15]Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Defect diagnosis based on DFM guidelines. VTS 2010: 206-211 - 2009
- [c14]M. Enamul Amyeen, Srikanth Venkataraman, Mun Wai Mak:
Microprocessor system failures debug and fault isolation methodology. ITC 2009: 1-10 - 2008
- [c13]Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman:
Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects. ATS 2008: 217-220 - 2007
- [c12]Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau:
Testing for systematic defects based on DFM guidelines. ITC 2007: 1-10 - [c11]Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang:
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. VTS 2007: 231-238 - 2006
- [c10]M. Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman:
Improving Precision Using Mixed-level Fault Diagnosis. ITC 2006: 1-10 - [c9]Ruifeng Guo, Subhasish Mitra, M. Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman:
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. VTS 2006: 66-71 - [c8]Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399 - 2004
- [c7]M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee:
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. ITC 2004: 669-678 - [c6]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen:
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480 - [c5]Srikanth Venkataraman, Srihari Sivaraj, M. Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo:
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. VTS 2004: 23-30 - 2003
- [c4]Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. VTS 2003: 351-358 - 2002
- [c3]M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs:
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. VTS 2002: 181-186 - 2001
- [c2]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. VTS 2001: 124-130 - 1999
- [c1]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Implication and Evaluation Techniques for Proving Fault Equivalence. VTS 1999: 201-213
Coauthor Index
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