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ORCIDJyoti Patel
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2020 – today
- 2024
[j2]Shubham Saini
, Jyoti Patel, Renu Garg:
Statistical inference on multicomponent stress-strength reliability with non-identical component strengths using progressively censored data from Kumaraswamy distribution. Soft Comput. 28(17-18): 9317-9339 (2024)- [c8]Jyoti Patel, Navjeet Bagga, Vivek Kumar, S. Dasgupta:
Small Signal Analysis of Nanosheet Transistor for sub-THz Frequency Considering Intersheet Capacitances and Modified Admittance Parameters. DRC 2024: 1-2 - [c7]Jyoti Patel, Soumen Mandal, Malay Bhattacharyya:
Judgment Analysis in a Streaming Setting Incurring Logarithmic Space of the Annotators. ICPR (24) 2024: 1-15 - [c6]Jyoti Patel, Sankalp Rai, Vivek Kumar, Sudeb Dasgupta:
Interface Trap Analysis in Multi-Fin FinFET Technology: a Crucial Reliability Issue in Digital Application. ISCAS 2024: 1-5 - [c5]Vivek Kumar, Nischal Anand, Rohit Rai, Sneha Chauhan, Jyoti Patel:
Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective. VLSID 2024: 49-54 - [i1]Akanksha Das, Jyoti Patel, Malay Bhattacharyya:
Aggregation of Constrained Crowd Opinions for Urban Planning. CoRR abs/2410.02454 (2024) - 2023
- [c4]Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta:
Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. APCCAS 2023: 90-94 - [c3]Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta:
FEM modeling of gate resistance for 5 nm SGC/DGC Stacked Nanosheet Transistor. VLSID 2023: 1-6 - [d1]Dhrumil Patel, Akshara Mehta, Mallikarjun Bhusnoor, Jyoti Patel, Sandeep Sainkar, Ninad Mehendale:
Dronevision: A Dataset of Aerial Videos for Computer Vision Applications. IEEE DataPort, 2023
- 2022
- [c2]Vivek Kumar, Jyoti Patel, Arnab Datta, Sudeb Dasgupta:
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet. VDAT 2022: 3-11 - [c1]Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta:
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID 2022: 292-296
2010 – 2019
- 2019
- [j1]Jyoti Patel, Dheeraj Sharma, Shivendra Yadav, Alemienla Lemtur, Priyanka Suman:
Performance improvement of nano wire TFET by hetero-dielectric and hetero-material: At device and circuit level. Microelectron. J. 85: 72-82 (2019)
Coauthor Index
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