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2020 – today
- 2024
[j5]Jhilam Jana, Ritesh Sur Chowdhury, Sayan Tripathi, Jaydeb Bhaumik:
FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT. J. Real Time Image Process. 21(1): 19 (2024)- [j4]Ritesh Sur Chowdhury
, Jhilam Jana, Sayan Tripathi, Jaydeb Bhaumik:
Improved DWT and IDWT architectures for image compression. Microprocess. Microsystems 104: 104990 (2024) - 2023
- [j3]Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik:
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application. Integr. 89: 56-72 (2023) - [i2]Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik:
Implementation of Fast and Power Efficient SEC-DAEC and SEC-DAEC-TAEC Codecs on FPGA. CoRR abs/2307.16195 (2023) - 2020
- [j2]Raj Kumar Maity, Sayan Tripathi, Jagannath Samanta, Jaydeb Bhaumik:
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs. IET Comput. Digit. Tech. 14(5): 210-216 (2020) - [i1]Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik:
Design of SEC-DED and SEC-DED-DAEC Codes of different lengths. CoRR abs/2002.07507 (2020)
2010 – 2019
- 2019
- [j1]Jagannath Samanta, Sayan Tripathi:
Comments on "a novel approach of error detection and correction for efficient energy in wireless networks". Multim. Tools Appl. 78(6): 7579-7584 (2019) - [c2]Jhilam Jana, Sayan Tripathi, Asim Kumar Jana, Malay Kumar Pandit:
Design and Development of Electronics Pest Repellent Using PIR Sensor and 8051 Micro-Controller. ICITAM 2019: 758-766 - [c1]Sayan Tripathi, Jhilam Jana, Jagannath Samanta, Jaydeb Bhaumik:
Fast and Power Efficient SEC-DED and SEC-DED-DAEC Codes in IoT based Wireless Sensor Networks. TENCON 2019: 540-545
Coauthor Index
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