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Journal Articles

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2012
[j2]
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Khaled R. Heloue, Sari Onaissi, Farid N. Najm:
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 472-484 (2012)
2008
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Sari Onaissi, Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1291-1304 (2008)

Conference and Workshop Papers

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2011
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Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm:
A fast approach for static timing analysis covering all PVT corners. DAC 2011: 777-782
2009
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Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
Clock skew optimization via wiresizing for timing sign-off covering all process corners. DAC 2009: 196-201
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Sari Onaissi, Khaled R. Heloue, Farid N. Najm:
PSTA-based branch and bound approach to the silicon speedpath isolation problem. ICCAD 2009: 217-224
2008
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Khaled R. Heloue, Sari Onaissi, Farid N. Najm:
Efficient block-based parameterized timing analysis covering all potentially critical paths. ICCAD 2008: 173-180
2006
[c1]
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Sari Onaissi, Farid N. Najm:
A linear-time approach for static timing analysis covering all process corners. ICCAD 2006: 217-224

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