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ORCIDYasushi Yuminaka
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2020 – today
- 2024
[j17]Yasushi Yuminaka:
Foreword. IEICE Trans. Inf. Syst. 107(8): 912 (2024)- [j16]Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka:
Evaluation of Multi-Valued Data Transmission in Two-Dimensional Symbol Mapping using Linear Mixture Model. IEICE Trans. Inf. Syst. 107(8): 976-984 (2024) - [j15]Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima:
Evaluating PAM-4 Data Transmission Quality Using Multi-Dimensional Mapping of Received Symbols. IEICE Trans. Inf. Syst. 107(8): 985-991 (2024) - [c29]Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato:
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. IJCNN 2024: 1-6 - [c28]Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka:
Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping. ISMVL 2024: 19-24 - [c27]Yasushi Yuminaka, Hayate Hasegawa, Nagito Ishida, Yosuke Iijima:
Specialized Waveform Equalization Techniques for Multi-Valued Data Transmission. ISMVL 2024: 25-29 - 2023
- [j14]Kazuharu Nakajima, Yasushi Yuminaka, Yosuke Iijima:
Multi-Valued Data Transmission Quality Evaluation Using Two-Dimensional PAM-4 Symbol Mapping. FLAP 10(6): 973-991 (2023) - [c26]Yasushi Yuminaka, Kazuharu Nakajima, Yosuke Iijima:
PAM-4 Data Transmission Quality Evaluation Using Two- and Three-Dimensional Mapping of Received Symbols. ISMVL 2023: 94-98 - [c25]Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka:
Evaluation and Symbol Classification of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping with Linear Mixture Model. ISMVL 2023: 99-104 - 2022
- [j13]Yosuke Iijima, Yasushi Yuminaka:
Efficient PAM-4 Symbol Estimation Using Soft Clustering. FLAP 9(3): 675-690 (2022) - [c24]Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas:
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN 2022: 1-7 - [c23]Yosuke Iijima, Kazuharu Nakajima, Yasushi Yuminaka:
Two-Dimensional Symbol Mapping for Evaluating Multi-Valued Data Transmission Quality. ISMVL 2022: 170-175 - 2021
- [j12]Yosuke Iijima, Keigo Taya, Yasushi Yuminaka
:
PAM-4 Eye-Opening Monitor Technique Using Gaussian Mixture Model for Adaptive Equalization. IEICE Trans. Inf. Syst. 104-D(8): 1138-1145 (2021) - [c22]Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas:
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) 2021: 177-181 - [c21]Yosuke Iijima, Yasushi Yuminaka:
Efficient PAM-4 Data Transmission with Closed Eye Using Symbol Distribution Estimation. ISMVL 2021: 195-200 - 2020
- [j11]Yasushi Yuminaka, Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima:
PAM-4 Signal Transmitter using FPGA and DAC for Serial-link Test. FLAP 7(1): 29-40 (2020) - [j10]Keigo Taya, Yasushi Yuminaka, Yosuke Iijama:
Statistical Waveform Evaluation Method for Adaptive PAM-4 Equalization. FLAP 8(5): 1087-1100 (2020) - [c20]Yosuke Iijima, Keigo Taya, Yasushi Yuminaka:
PAM-4 Eye-Opening Monitoring Techniques Using Gaussian Mixture Model. ISMVL 2020: 149-154
2010 – 2019
- 2019
- [c19]Yosuke Iijima, Yasushi Yuminaka:
Waveform Shaping Transmitter Combining Digital and Analog Circuits for Multi - Valued Signaling. ISMVL 2019: 19-24 - 2018
- [c18]Natsuki Sato, Takahito Chigira, Kohei Toyoda, Yosuke Iijima, Yasushi Yuminaka:
Multi-valued Signal Generation and Measurement for PAM-4 Serial-Link Test. ISMVL 2018: 210-214 - 2017
- [j9]Yosuke Iijima, Yasushi Yuminaka:
Double-Rate Tomlinson-Harashima Precoding for Multi-Valued Data Transmission. IEICE Trans. Inf. Syst. 100-D(8): 1611-1617 (2017) - [c17]Yasushi Yuminaka, Takuya Kitamura, Yosuke Iijima:
PAM-4 Eye Diagram Analysis and Its Monitoring Technique for Adaptive Pre-Emphasis for Multi-valued Data Transmissions. ISMVL 2017: 13-18 - 2016
- [j8]Yasushi Yuminaka, Yosuke Iijima:
Multiple-Valued Signaling for High-Speed Serial Links Using Tomlinson-Harashima Precoding. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 25-33 (2016) - [j7]Yasushi Yuminaka, Yuuki Takada, Tomonao Okada:
Comparison of Spectrally Efficient Coding Techniques for High-Speed VLSI Data Transmission. J. Multiple Valued Log. Soft Comput. 26(1-2): 75-87 (2016) - [c16]Yosuke Iijima, Yasushi Yuminaka:
Double-Rate Equalization Using Tomlinson-Harashima Precoding for Multi-valued Data Transmission. ISMVL 2016: 66-71 - 2014
- [j6]Yosuke Iijima, Yuki Takada, Yasushi Yuminaka:
High-Speed Interconnection for VLSI Systems Using Multiple-Valued Signaling with Tomlinson-Harashima Precoding. IEICE Trans. Inf. Syst. 97-D(9): 2296-2303 (2014) - [c15]Yosuke Iijima, Yasushi Yuminaka:
Evaluation of High-Speed Interfaces for VLSI Systems Using Tomlinson-Harashima Precoding. ISMVL 2014: 138-143 - [c14]Yasushi Yuminaka, Yuki Takada, Tomonao Okada, Yosuke Iijima:
Comparison of Spectrally Efficient Coding Techniques for High-Speed Serial Links. ISMVL 2014: 150-154 - 2012
- [j5]Yasushi Yuminaka, Kyohei Kawano:
A Bandwidth-Efficient Ternary Signaling Scheme for 1-D Partial-Response Channels. J. Multiple Valued Log. Soft Comput. 19(1-3): 271-282 (2012) - [c13]Yasushi Yuminaka, Masaaki Okui:
Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation. ISMVL 2012: 7-12 - 2010
- [j4]Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi:
Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques. IEICE Trans. Inf. Syst. 93-D(8): 2109-2116 (2010) - [c12]Yasushi Yuminaka, Kyohei Kawano:
A Ternary Partial-Response Signaling Scheme for Capacitively Coupled Interface. ISMVL 2010: 331-336
2000 – 2009
- 2009
- [j3]Yasushi Yuminaka, Yasunori Takahashi:
Time-Domain Pre-Emphasis Techniques for Multiple Valued Data Transmission. J. Multiple Valued Log. Soft Comput. 15(4): 301-313 (2009) - [c11]Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi:
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. ISMVL 2009: 250-255 - 2008
- [c10]Yasushi Yuminaka, Yasunori Takahashi:
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. ISMVL 2008: 20-25 - 2007
- [j2]Yasushi Yuminaka, Kazuyoshi Yamamura:
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. J. Multiple Valued Log. Soft Comput. 13(4-6): 569-582 (2007) - [c9]Yasushi Yuminaka, Kazuyoshi Yamamura:
Equalization Techniques for Multiple-Valued Data Transmission and Their Application. ISMVL 2007: 26 - 2005
- [j1]Yasushi Yuminaka:
Intra/Inter-Chip CDMA Communications for Efficient Data Transmission Towards New Paradigm of Computing. J. Multiple Valued Log. Soft Comput. 11(5-6): 603-618 (2005) - 2002
- [c8]Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi:
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. ISMVL 2002: 54-60 - 2000
- [c7]Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. ISMVL 2000: 430-437
1990 – 1999
- 1999
- [c6]Mohd Asmawi Mohamed Zin, Haruo Kobayashi, Kazuya Kobayashi, Jun-ichi Ichimura, Hao San, Yoshitaka Onaya, Yasuyuki Kimura, Yasushi Yuminaka, Yoshisato Sasaki, Kouji Tanaka, Fuminori Abe:
A high-speed CMOS track/hold circuit. ICECS 1999: 1709-1712 - 1998
- [c5]Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. ISMVL 1998: 148-154 - 1996
- [c4]Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. ISMVL 1996: 210-215 - 1994
- [c3]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. ISMVL 1994: 207-214 - 1993
- [c2]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of Set-Valued Logic Networks for Wave-Parallel Computing. ISMVL 1993: 277-282 - 1991
- [c1]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. ISMVL 1991: 8-15
Coauthor Index
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