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ORCIDSai Lalith Chaitanya Ambatipudi
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Journal Articles
- 2020
[j1]Mayank Raj
, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE J. Solid State Circuits 55(4): 1086-1095 (2020)
Conference and Workshop Papers
- 2020
- [c5]Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. ECOC 2020: 1-4 - 2019
- [c4]Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. VLSI Circuits 2019: 190- - 2018
- [c3]Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112-GB/S PAM4 Transmitter in 16NM FinFET. VLSI Circuits 2018: 45-46 - [c2]James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits 2018: 47-48 - [c1]Kevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann:
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. VLSI Circuits 2018: 269-270
Coauthor Index
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