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ORCIDAmir M. Hajisadeghi
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2020 – today
- 2024
[j3]Amir M. Hajisadeghi
, Mahmoud Momtazpour, Hamid R. Zarandi:
Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. Future Gener. Comput. Syst. 160: 40-53 (2024)- [i2]Ali Sedaghatgoo, Amir M. Hajisadeghi, Mahmoud Momtazpour, Nader Bagherzadeh:
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks. CoRR abs/2402.04431 (2024) - [i1]Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour:
Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM. CoRR abs/2411.19344 (2024) - 2022
- [c5]Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi:
EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. DSD 2022: 32-38 - 2021
- [j2]Amir M. Hajisadeghi, Hamid R. Zarandi:
CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. Microprocess. Microsystems 85: 104282 (2021) - 2020
- [j1]Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi:
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. Microprocess. Microsystems 73: 102963 (2020)
2010 – 2019
- 2019
- [c4]Salar Hashemi, Amir M. Hajisadeghi, Hamid R. Zarandi, Saadat Pour-Mozafari:
A Fast and Efficient Fault Tree Analysis Using Approximate Computing. EDCC 2019: 39-46 - 2018
- [c3]Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi:
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. DSD 2018: 182-189 - [c2]Amir M. Hajisadeghi, Hossein Bardareh, Hamid R. Zarandi:
MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. DSD 2018: 237-243 - [c1]Hossein Bardareh, Amir M. Hajisadeghi, Hamid R. Zarandi:
A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. IOLTS 2018: 39-40
Coauthor Index
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