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2020 – today
- 2020
[j6]Dam Minh Tung
, Nguyen Van Toan, Jeong-Gun Lee:
In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA. J. Circuits Syst. Comput. 29(6): 2050098:1-2050098:22 (2020)
2010 – 2019
- 2019
- [j5]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA. Comput. Electr. Eng. 74: 149-163 (2019) - [j4]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
A GALS design based on multi-frequency clocking for digital switching noise reduction. Integr. 69: 210-224 (2019) - [j3]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation. J. Circuits Syst. Comput. 28(1): 1950018:1-1950018:23 (2019) - 2018
- [j2]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Measurements of metastability in MUTEX on an FPGA. IEICE Electron. Express 15(1): 20171165 (2018) - [j1]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1685-1698 (2018) - [c3]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction. APCCAS 2018: 287-290 - 2017
- [c2]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
Exploring the current consumption of an Intel Edison module for IoT applications. I2MTC 2017: 1-6 - [c1]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Energy-efficient and high performance 2-phase asynchronous micropipelines. MWSCAS 2017: 1188-1191
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