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Journal Articles
- 2018
[j1]Matheus T. Moreira, Peter A. Beerel, Marcos L. L. Sartori
, Ney Laert Vilar Calazans:
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1981-1993 (2018)
Conference and Workshop Papers
- 2023
- [c9]Willian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans:
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V. SBCCI 2023: 1-6 - 2022
- [c8]Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans:
Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. ISCAS 2022: 1269-1273 - [c7]Marcos Luiggi Lemos Sartori, Willian Analdo Nunes, Ney Laert Vilar Calazans:
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design. SBCCI 2022: 1-6 - 2021
- [c6]Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. ISCAS 2021: 1-5 - 2020
- [c5]Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ASYNC 2020: 3-10 - [c4]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans:
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ISCAS 2020: 1-5 - 2019
- [c3]Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans:
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ASYNC 2019: 114-123 - [c2]Rodrigo N. Wuerdig, Marcos L. L. Sartori, Ney Laert Vilar Calazans:
Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations. LASCAS 2019: 137-140 - 2017
- [c1]Marcos L. L. Sartori, Ney Laert Vilar Calazans:
Go functional model for a RISC-V asynchronous organisation - ARV. ICECS 2017: 381-384
Coauthor Index
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