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D. Tretyakov

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2010 – 2019

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2018
[c2]
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  - conf/ewdts/OstaninABT18
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  persistent URL:
  - https://dblp.org/rec/conf/ewdts/OstaninABT18
Sergey Ostanin, Valentina Andreeva, Natalia Butorina, D. Tretyakov:
Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults. EWDTS 2018: 1-4
2017
[c1]
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Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina:
Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS 2017: 1-4

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