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Journal Articles
- 2002
[j1]Yih-Chih Chou, Youn-Long Lin:
Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 15-22 (2002)
Conference and Workshop Papers
- 2020
- [c8]Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai:
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. ICCAD 2020: 156:1-156:9 - [c7]Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao:
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. ISPD 2020: 57-64 - 2019
- [c6]Yih-Chih Chou, Chien-Cheng Wu, Cheng-Hong Tsai:
Clocking for HPC Design: Challenges and Experience Sharing. VLSI-DAT 2019: 1-2 - 2016
- [c5]Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou:
Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS 2016: 2591-2594 - 2001
- [c4]Yih-Chih Chou, Youn-Long Lin:
A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191 - [c3]Yih-Chih Chou, Youn-Long Lin:
A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29 - 1998
- [c2]Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin:
Integrating logic retiming and register placement. ICCAD 1998: 136-139 - [c1]Yih-Chih Chou, Youn-Long Lin:
A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429
Coauthor Index
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