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ORCIDNaveed Riaz
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2020 – today
- 2024
[j5]Faiza Eba Batool, Muhammad Attique Khan, Muhammad Sharif, Kashif Javed, Muhammad Nazir, Aaqif Afzaal Abbasi
, Zeshan Iqbal, Naveed Riaz:
Offline signature verification system: a novel technique of fusion of GLCM and geometric features using SVM. Multim. Tools Appl. 83(5): 14959-14978 (2024)- [j4]Asif Mehmood, Muhammad Attique Khan, Muhammad Sharif, Sajid Ali Khan, Muhammad Shaheen, Tanzila Saba, Naveed Riaz, Imran Ashraf:
Prosperous Human Gait Recognition: an end-to-end system based on pre-trained CNN features selection. Multim. Tools Appl. 83(5): 14979-14999 (2024) - [p2]Faisal Rehman, Hanan Sharif, Muhammad Anwar, Naveed Riaz:
Big Data Analytics for Cybersecurity in IoE Networks. Cybersecurity Vigilance and Security Engineering of Internet of Everything 2024: 163-176 - [i1]Mahnoor Naseer, Sundas Tariq, Naveed Riaz, Naveed Ahmed, Mureed Hussain:
S-box Security Analysis of NIST Lightweight Cryptography Candidates: A Critical Empirical Study. CoRR abs/2404.06094 (2024) - 2023
- [j3]Zainab Akhtar, Jong Weon Lee, Muhammad Attique Khan, Muhammad Sharif, Sajid Ali Khan, Naveed Riaz:
Optical character recognition (OCR) using partial least square (PLS) based feature reduction: an application to artificial intelligence for biometric identification. J. Enterp. Inf. Manag. 36(3): 767-789 (2023)
2010 – 2019
- 2018
- [j2]Adeel-ur-Rehman, Naveed Riaz:
Advanced architecture for java universal message passing (AA-JUMP). Int. Arab J. Inf. Technol. 15(3): 429-434 (2018) - 2012
- [j1]Bernhard Peischl, Naveed Riaz, Franz Wotawa:
Automated Debugging of Verilog Designs. Int. J. Softw. Eng. Knowl. Eng. 22(5): 695- (2012) - 2011
- [c3]Mehnaz Hafeez, Sajjad Asghar, Usman Ahmad Malik, Adeel-ur-Rehman, Naveed Riaz:
Survey of MPI Implementations. DICTAP (2) 2011: 206-220 - 2010
- [c2]Sajjad Asghar, Mehnaz Hafeez, Usman Ahmad Malik, Adeel-ur-Rehman, Naveed Riaz:
A-JUMP, architecture for Java universal message passing. FIT 2010: 34
2000 – 2009
- 2009
- [c1]Bernhard Peischl, Naveed Riaz, Franz Wotawa:
Employing Test Suites for Verilog Fault Localization. CAEPIA 2009: 1-10 - 2008
- [p1]Bernhard Peischl, Naveed Riaz, Franz Wotawa:
Advances in Automated Source-Level Debugging of Verilog Designs. New Challenges in Applied Intelligence Technologies 2008: 363-372
Coauthor Index
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last updated on 2024-10-07 22:16 CEST by the dblp team
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