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Books and Theses
- 2024
[b1]Johannes Schreiner:
Model-based Generation of Highly Configurable RTL Designs. Technical University of Munich, Germany, 2024
Conference and Workshop Papers
- 2023
- [c5]Johannes Schreiner, Vasundhara Raje Gontia, Sebastian Prebeck, Wolfgang Ecker:
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation. MBMV 2023: 1-12 - 2017
- [c4]Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Python based framework for HDSLs with an underlying formal semantics: (Invited paper). ICCAD 2017: 1019-1025 - 2016
- [c3]Johannes Schreiner, Rainer Findenig, Wolfgang Ecker:
Design centric modeling of digital hardware. HLDVT 2016: 46-52 - [c2]Wolfgang Ecker, Johannes Schreiner:
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. VLSI-SoC 2016: 1-6 - [c1]Johannes Schreiner, Wolfgang Ecker:
Digital Hardware Design Based on Metamodels and Model Transformations. VLSI-SoC (Selected Papers) 2016: 83-107
Parts in Books or Collections
- 2017
- [p1]Wolfgang Ecker, Johannes Schreiner:
Metamodeling and Code Generation in the Hardware/Software Interface Domain. Handbook of Hardware/Software Codesign 2017: 1051-1091
Informal and Other Publications
- 2024
- [i1]Johannes Schreiner, Daniel Gerl, Robert Kunzelmann, Paritosh Kumar Sinha, Wolfgang Ecker:
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. CoRR abs/2404.05599 (2024)
Coauthor Index
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last updated on 2024-07-11 20:18 CEST by the dblp team
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