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2020 – today
- 2022
[j9]Bor-Sen Chen
, Po-Hsun Wu:
Robust H∞ Observer-Based Reference Tracking Control Design of Nonlinear Stochastic Systems: HJIE-Embedded Deep Learning Approach. IEEE Access 10: 39889-39911 (2022)- 2021
- [j8]Bor-Sen Chen, Po-Hsun Wu, Min-Yen Lee:
Robust H∞ Deep Neural Network-Based Filter Design of Nonlinear Stochastic Signal Systems. IEEE Access 9: 165103-165119 (2021)
2010 – 2019
- 2019
- [c9]Po-Hsun Wu, Chun-Jen Weng, Pi-Ying Cheng:
Auto-focus pathology microscope using sub-array sampling. I2MTC 2019: 1-5 - 2016
- [j7]Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho:
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching. ACM Trans. Design Autom. Electr. Syst. 21(3): 39:1-39:22 (2016) - 2015
- [j6]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho:
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(2): 199-212 (2015) - [c8]Po-Hsun Wu, Mark Po-Hung Lin, Tsung-Yi Ho:
Analog layout synthesis with knowledge mining. ECCTD 2015: 1-4 - [c7]Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho:
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment. ISPD 2015: 25-31 - 2014
- [j5]Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho:
Placement optimization of flexible TFT circuits with mechanical strain and temperature consideration. ACM J. Emerg. Technol. Comput. Syst. 11(1): 1:1-1:28 (2014) - [j4]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu:
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 879-892 (2014) - [c6]Po-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho:
A topology-based ECO routing methodology for mask cost minimization. ASP-DAC 2014: 507-512 - [c5]Po-Hsun Wu, Che-Wen Chen, Chi-Ruo Wu, Tsung-Yi Ho:
Triangle-based process hotspot classification with dummification in EUVL. VLSI-DAT 2014: 1-4 - 2013
- [j3]Po-Hsun Wu, Tsung-Yi Ho:
Bus-driven floorplanning with thermal consideration. Integr. 46(4): 369-381 (2013) - [j2]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin:
1-D Cell Generation With Printability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 419-432 (2013) - [c4]Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho:
A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration. ASP-DAC 2013: 491-496 - [c3]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen:
Lithography-aware 1-dimensional cell generation. ECCTD 2013: 1-4 - 2012
- [j1]Po-Hsun Wu, Tsung-Yi Ho:
Bus-driven floorplanning with bus pin assignment and deviation minimization. Integr. 45(4): 405-426 (2012) - [c2]Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu:
Performance-driven analog placement considering monotonic current paths. ICCAD 2012: 613-619 - 2011
- [c1]Po-Hsun Wu, Tsung-Yi Ho:
Thermal-aware bus-driven floorplanning. ISLPED 2011: 205-210
Coauthor Index
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