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ORCIDMikael Millberg
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Books and Theses
- 2011
[b1]Mikael Millberg:
Architectural Techniques for Improving Performance in Networks on Chip. Royal Institute of Technology, Stockholm, Sweden, 2011
Journal Articles
- 2004
- [j3]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen:
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integr. 38(1): 3-17 (2004) - 2000
- [j2]Joakim Waldemark, Mikael Millberg, Thomas Lindblad, Karina Waldemark, Vlatko Becanovic:
Implementation Of A Pulse Coupled Neural Network in FPGA. Int. J. Neural Syst. 10(3): 171-177 (2000) - [j1]Joakim Waldemark, Mikael Millberg, Thomas Lindblad, Karina Waldemark:
Image analysis for airborne reconnaissance and missile applications. Pattern Recognit. Lett. 21(3): 239-251 (2000)
Conference and Workshop Papers
- 2009
- [c10]Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson:
Flow regulation for on-chip communication. DATE 2009: 578-581 - [c9]Mikael Millberg, Axel Jantsch
:
Priority based forced requeue to reduce worst-case latencies for bursty traffic. DATE 2009: 1070-1075 - 2007
- [c8]Mikael Millberg, Axel Jantsch:
Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy. DSD 2007: 511-518 - [c7]Mikael Millberg, Axel Jantsch:
A Study of NoC Exit Strategies. NOCS 2007: 217 - 2004
- [c6]Mikael Millberg, Erland Nilsson, Rikard Thid, Axel Jantsch:
Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. DATE 2004: 890-895 - [c5]Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch:
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. VLSI Design 2004: 693-696 - 2003
- [c4]Erland Nilsson, Mikael Millberg, Johnny Öberg, Axel Jantsch:
Load Distribution with the Proximity Congestion Awareness in a Network on Chip. DATE 2003: 11126-11127 - [c3]Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch:
Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362- - 2002
- [c2]Per Bjuréus, Mikael Millberg, Axel Jantsch:
FPGA resource and timing estimation from Matlab execution traces. CODES 2002: 31-36 - [c1]Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani:
A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124
Coauthor Index
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