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2010 – 2019
- 2017
[j6]Sudhanshu Shekhar Jha, Wim Heirman
, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. 100: 30-41 (2017)- 2016
- [c14]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout:
Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers 2016: 365-368 - 2015
- [c13]Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout:
Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers 2015: 19:1-19:8 - 2014
- [c12]Alex Ramírez, Ayose Falcón, Oliverio J. Santana, Mateo Valero:
Author retrospective for software trace cache. ICS 25th Anniversary 2014: 45-47
2000 – 2009
- 2009
- [j5]Matteo Monchiero, Jung Ho Ahn, Ayose Falcón, Daniel Ortega, Paolo Faraboschi:
How to simulate 1000 cores. SIGARCH Comput. Archit. News 37(2): 10-19 (2009) - [j4]Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, Matteo Monchiero, Daniel Ortega:
COTSon: infrastructure for full system simulation. ACM SIGOPS Oper. Syst. Rev. 43(1): 52-61 (2009) - [j3]Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero:
DIA: A Complexity-Effective Decoding Architecture. IEEE Trans. Computers 58(4): 448-462 (2009) - [c11]Diego Lugones, Daniel Franco, Dolores Rexachs, Juan C. Moure, Emilio Luque, Eduardo Argollo, Ayose Falcón, Daniel Ortega, Paolo Faraboschi:
High-speed network modeling for full system simulation. IISWC 2009: 24-33 - 2008
- [c10]Ayose Falcón, Paolo Faraboschi, Daniel Ortega:
An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters. ISPASS 2008: 22-31 - 2007
- [c9]Ayose Falcón, Paolo Faraboschi, Daniel Ortega:
Combining Simulation and Virtualization through Dynamic Sampling. ISPASS 2007: 72-83 - 2006
- [c8]Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero:
Branch predictor guided instruction decoding. PACT 2006: 202-211 - 2005
- [j2]Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero:
Better Branch Prediction Through Prophet/Critic Hybrids. IEEE Micro 25(1): 80-89 (2005) - [c7]Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero:
A Complexity-Effective Simultaneous Multithreading Architecture. ICPP 2005: 157-164 - [c6]Ayose Falcón, Alex Ramírez, Mateo Valero:
Effective Instruction Prefetching via Fetch Prestaging. IPDPS 2005 - 2004
- [j1]Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero:
A latency-conscious SMT branch prediction architecture. Int. J. High Perform. Comput. Netw. 2(1): 11-21 (2004) - [c5]Ayose Falcón, Alex Ramírez, Mateo Valero:
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. HPCA 2004: 244-253 - [c4]Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero:
Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263 - 2003
- [c3]Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero:
Tolerating Branch Predictor Latency on SMT. ISHPC 2003: 86-98 - 2002
- [c2]Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero:
A Comprehensive Analysis of Indirect Branch Prediction. ISHPC 2002: 133-145 - [c1]Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero:
Studying New Ways for Improving Adaptive History Length Branch Predictors. ISHPC 2002: 271-280
Coauthor Index
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