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ORCIDXu Han 0002
Person information
- affiliation: University of California, Irvine, Center for Embedded Computer Systems, CA, USA
Other persons with the same name
- Xu Han — disambiguation page
- Xu Han 0001 — University of Connecticut, School of Electrical and Computer Engineering, Storrs, CT, USA
- Xu Han 0003
![[0000-0003-3707-660X]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-3707-660X")
— Beijing University of Posts and Telecommunications, School of Software Engineering, Key Laboratory of Trustworthy Distributed Computing and Service, China - Xu Han 0004 — Southwestern University of Finance and Economics, School of Economic Mathematics / School of Finance, Chengdu, China
- Xu Han 0005 — Jilin University, College of Computer Science and Technology, Changchun, China
- Xu Han 0006 — University of Colorado Boulder, CO, USA
- Xu Han 0007 — Tsinghua University, Department of Computer Science and Technology, China
- Xu Han 0008 — Nanyang Technological University, School of Computer Engineering, Singapore
- Xu Han 0009 — University of North Carolina at Chapel Hill, UNC, Department of Computer Science, USA
- Xu Han 0010 — Northwestern Polytechnical University, Department of Electrical Engineering, Xi'an, China
- Xu Han 0011 — Hebei University of Technology, State Key Laboratory of Reliability and Intelligence of Electrical Equipment, School of Mechanical Engineering, Tianjin, China (and 1 more)
- Xu Han 0012 — Tufts University, Department of Computer Science, Medford, MA, USA
- Xu Han 0013 — Beihang University, School of Transportation Science and Engineering, Beijing, China
- Xu Han 0014 — University of California, Los Angeles, UCLA, Department of Civil and Environmental Engineering, CA, USA
- Xu Han 0015 — Hubei University of Technology, School of Industrial Design, Wuhan, China
- Xu Han 0016 — Huazhong University of Science and Technology, China (and 1 more)
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2010 – 2019
- 2014
[j3]Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer:
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1859-1872 (2014)- [c7]Weiwei Chen, Xu Han, Rainer Dömer:
May-happen-in-parallel analysis based on segment graphs for safe ESL models. DATE 2014: 1-6 - 2013
- [j2]Weiwei Chen, Xu Han, Che-Wei Chang, Rainer Dömer:
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. IEEE Des. Test 30(1): 45-54 (2013) - [c6]Xu Han, Weiwei Chen, Rainer Dömer:
Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. M-SCOPES 2013: 40-47 - 2012
- [c5]Rainer Dömer, Weiwei Chen, Xu Han:
Parallel discrete event simulation of Transaction Level Models. ASP-DAC 2012: 227-231 - [c4]Weiwei Chen, Xu Han, Rainer Dömer:
Out-of-order parallel simulation for ESL design. DATE 2012: 141-146 - [c3]Weiwei Chen, Che-Wei Chang, Xu Han, Rainer Dömer:
Eliminating race conditions in system-level models by using parallel simulation infrastructure. HLDVT 2012: 118-123 - 2011
- [j1]Weiwei Chen, Xu Han, Rainer Dömer:
Multicore Simulation of Transaction-Level Models Using the SoC Environment. IEEE Des. Test Comput. 28(3): 20-31 (2011) - [c2]Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer:
Multi-core parallel simulation of System-level Description Languages. ASP-DAC 2011: 311-316 - 2010
- [c1]Weiwei Chen, Xu Han, Rainer Dömer:
ESL design and multi-core validation using the System-on-Chip Environment. HLDVT 2010: 142-147
Coauthor Index
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