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Chuan-Kang Liang

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2000 – 2009

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2008
[j2]
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Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu:
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(1): 361-369 (2008)
2006
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Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu:
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. IEEE J. Solid State Circuits 41(6): 1380-1390 (2006)

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