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ORCIDKleanthis Papachatzopoulos
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Journal Articles
- 2023
[j5]Kleanthis Papachatzopoulos
, Vassilis Paliouras:
Path-Based Delay Variation Models for Parallel-Prefix Adders. IEEE Trans. Emerg. Top. Comput. 11(3): 689-705 (2023)- [j4]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams. IEEE Trans. Emerg. Top. Comput. 11(4): 1002-1017 (2023) - 2021
- [j3]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. IEEE Trans. Emerg. Top. Comput. 9(3): 1479-1488 (2021) - 2019
- [j2]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2546-2559 (2019) - 2018
- [j1]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 572-576 (2018)
Conference and Workshop Papers
- 2022
- [c6]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees. ISCAS 2022: 924-928 - 2021
- [c5]Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
Sum Propagate Adders. ARITH 2021: 110 - [c4]Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
A Novel Stochastic Polar Architecture for All-Digital Transmission. ISCAS 2021: 1-5 - 2020
- [c3]Kleanthis Papachatzopoulos, Vassilis Paliouras:
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations. ARITH 2020: 88-95 - [c2]Kleanthis Papachatzopoulos, Chris Andriakopoulos, Vassilis Paliouras:
Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering. ISCAS 2020: 1-5 - 2016
- [c1]Kleanthis Papachatzopoulos, Ioannis Kouretas, Vassilis Paliouras:
Dynamic delay variation behaviour of RNS multiply-add architectures. ISCAS 2016: 1978-1981
Coauthor Index
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