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Guenole Lallement
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2020 – today
- 2023
- [c7]Luke R. Upton, Guénolé Lallement, Michael D. Scott, Joyce Taylor, Robert M. Radway, Dennis Rich, Mark Nelson, Subhasish Mitra, Boris Murmann:
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices. ISQED 2023: 1-7 - 2022
- [j2]Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina:
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. IEEE J. Solid State Circuits 57(4): 1013-1026 (2022) - 2021
- [c6]Massimo Giordano, Kartik Prabhu, Kalhan Koul, Robert M. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina:
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. VLSI Circuits 2021: 1-2
2010 – 2019
- 2018
- [j1]Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran:
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI. IEEE J. Solid State Circuits 53(7): 2088-2100 (2018) - [c5]Guenole Lallement, Fady Abouzeid, Thierry Di Gilio, Philippe Roche, Jean-Luc Autran:
A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI. A-SSCC 2018: 197-200 - [c4]Yvan Debizet, Guénolé Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States. ISCAS 2018: 1-5 - 2017
- [c3]Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran:
A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking. A-SSCC 2017: 69-72 - [c2]Guenole Lallement, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Philippe Roche, Jean-Luc Autran:
A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI. ESSCIRC 2017: 153-162 - 2016
- [c1]Guenole Lallement, Nicolas Moser, Pantelis Georgiou:
Bio-inspired pH sensing using ion sensitive field effect transistors. ISCAS 2016: 2835-2838
Coauthor Index
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