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Yi-Ju Roh

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Journal Articles

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2020
[j3]
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  - journals/tcas/RohCR20
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  - https://dblp.org/rec/journals/tcas/RohCR20
Yi-Ju Roh, Dong-Jin Chang, Seung-Tak Ryu:
A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. IEEE Trans. Circuits Syst. 67-II(12): 2833-2837 (2020)
2018
[j2]
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Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu:
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1904-1908 (2018)
2016
[j1]
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Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu:
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits 51(8): 1826-1839 (2016)

Conference and Workshop Papers

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2019
[c1]
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Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu:
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits 2019: 138-

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