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2020 – today
- 2024
[j6]Rami Reddy Sowmya
, Arige Sumanth, Binsu J. Kailath, Tejendra Dixit:
Development of Accurate Model for Memristor-Based Filters and Oscillators: Amplitude, Frequency and Ramp-Rate Dependent Analysis. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 872-876 (2024)- [c11]Kavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal:
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks. DATE 2024: 1-2 - [c10]Bana Shanmuga Sai Badrinatha Reddy, Priya K, Binsu J. Kailath:
SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron. VDAT 2024: 1-6 - 2022
- [j5]Dinesh Ganesan, Binsu J. Kailath:
Graph-Based Circuit Simulator for Switched Capacitor Circuits. IEEE Des. Test 39(4): 81-89 (2022) - 2021
- [j4]Dinesh Ganesan, Binsu J. Kailath:
Tree/link method for transfer function and stability analysis of switched-capacitor circuits. Int. J. Circuit Theory Appl. 49(11): 3559-3582 (2021) - [j3]Sujitha S, Binsu J. Kailath:
High speed Power efficient Vedic arithmetic modules on Zedboard-Zynq-7000 FPGA. Int. J. Circuit Theory Appl. 49(11): 3683-3718 (2021) - [c9]Madhuvanthi Srivatsav R, Binsu J. Kailath:
A Novel Biphasic Neuron Encoder Implementation. AIIoT 2021: 226-231 - [c8]Sathiya Jothi. S, Binsu J. Kailath:
Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons. AIIoT 2021: 297-302 - 2020
- [c7]T. P. Shivangi, M. Rahimi, Gaetano D. Gargiulo, Binsu J. Kailath, Tara Julia Hamilton:
A Silicon Neuron-based Bio-Front-End for Ultra Low Power Bio-Monitoring at the Edge. SSCI 2020: 3043-3048 - [c6]Sai G. Pavan, Binsu J. Kailath:
Reusable Spiking Neural Network Architecture. UEMCON 2020: 614-620
2010 – 2019
- 2019
- [c5]Nithya K, Muralidhar Gadamsetty, Binsu J. Kailath:
FPGA Implementation of Speech Recognizer for Isolated Words. iSES 2019: 25-28 - 2018
- [j2]Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath:
PLL architecture with a composite PFD and variable loop filter. IET Circuits Devices Syst. 12(3): 256-262 (2018) - 2017
- [c4]K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath:
Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder. VDAT 2017: 36-47 - 2016
- [j1]Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath:
Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur. IEICE Electron. Express 13(10): 20160328 (2016) - [c3]Binsu J. Kailath, Dinesh Ganesan:
QSCsim - Charge Based Switched Capacitor Simulator. iNIS 2016: 284 - [c2]S. S. Karthikeyan, Dinesh Ganesan, Binsu J. Kailath:
Improved alias rejection using interleaved CIC decimation filter. NEWCAS 2016: 1-4 - [c1]G. Muralidhar, Dinesh Ganesan, Binsu J. Kailath:
Switched-capacitor circuit simulator in Q-V domain including nonidealities. VDAT 2016: 1-6
Coauthor Index
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last updated on 2024-11-21 21:22 CET by the dblp team
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