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S. Sioncke
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2010 – 2019
- 2018
- [c3]Vamsi Putcha, Jacopo Franco, Abhitosh Vais, Ben Kaczer, S. Sioncke, Dimitri Linten, Guido Groeseneken:
Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps. IRPS 2018: 5 - 2016
- [c2]Nadine Collaert, AliReza Alian, Hiroaki Arimura, Geert Boccardi, Geert Eneman, Jacopo Franco, Tsvetan Ivanov, Dennis Lin, Jérôme Mitard, S. Ramesh, R. Rooyackers, Marc Schaekers, A. Sibaya-Hernandez, S. Sioncke, Quentin Smets, Abhitosh Vais, A. Vandooren, Anabela Veloso, Anne S. Verhulst, Devin Verreck, Niamh Waldron, Amey Walke, Liesbeth Witters, H. Yu, X. Zhou, Aaron Voon-Yew Thean:
Beyond-Si materials and devices for more Moore and more than Moore applications. ICICDT 2016: 1-5 - 2015
- [c1]Abhitosh Vais, Koen Martens, Jacopo Franco, Dennis Lin, AliReza Alian, Philippe Roussel, S. Sioncke, Nadine Collaert, Aaron Thean, Marc M. Heyns, Guido Groeseneken, Kristin De Meyer:
The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. IRPS 2015: 5
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last updated on 2024-10-07 22:20 CEST by the dblp team
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