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ORCIDFahim U. Rahman
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- affiliation: University of Washington, Seattle, WA, USA
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2020 – today
- 2020
[j5]Fahim ur Rahman
, Rajesh Pamula, Visvesh S. Sathe:
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits 55(2): 494-504 (2020)
2010 – 2019
- 2019
- [j4]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54(4): 1173-1184 (2019) - [j3]Fahim ur Rahman, Greg Taylor, Visvesh Sathe:
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. IEEE J. Solid State Circuits 54(9): 2487-2500 (2019) - [j2]Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe:
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54(11): 3215-3225 (2019) - [c5]Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe:
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC 2019: 312-314 - 2018
- [j1]Fahim U. Rahman, Visvesh Sathe:
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. IEEE J. Solid State Circuits 53(3): 924-935 (2018) - [c4]Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe:
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC 2018: 302-304 - [c3]Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits 2018: 1-2 - [c2]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits 2018: 65-66 - 2016
- [c1]Fahim U. Rahman, Visvesh S. Sathe:
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. ISSCC 2016: 334-335
Coauthor Index
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