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ORCIDNaveen Kadayinti
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2020 – today
- 2023
[c5]Mayur S. Marinaik, Naveen Kadayinti:
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs. APCCAS 2023: 363-366- 2022
- [c4]Mayur S. Marinaik, Ganga K. Maheshwarappa, Naveen Kadayinti:
A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters. ISCAS 2022: 3473-3477
2010 – 2019
- 2018
- [j2]Naveen Kadayinti
, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects. Microelectron. J. 81: 101-106 (2018) - 2017
- [j1]Naveen Kadayinti, Dinesh Kumar Sharma:
Sense amplifier comparator with offset correction for decision feedback equalization based receivers. Microelectron. J. 70: 27-33 (2017) - [c3]Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma:
Settling time of mesochronous clock re-timing circuits in the presence of timing jitter. ISCAS 2017: 1-4 - [c2]Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects. VLSID 2017: 15-20 - [c1]Mahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma:
Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter. VLSID 2017: 321-326 - [i4]Naveen Kadayinti, Dinesh Kumar Sharma:
Sense Amplifier Comparator with Offset Correction for Decision Feedback Equalization based Receivers. CoRR abs/1702.01067 (2017) - 2016
- [i3]Naveen Kadayinti, Amitalok J. Budkuley, Dinesh Kumar Sharma:
Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects. CoRR abs/1604.00230 (2016) - 2015
- [i2]Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Clock Synchronizer for Repeaterless Low Swing On-Chip Links. CoRR abs/1510.04241 (2015) - [i1]Naveen Kadayinti, Dinesh Kumar Sharma:
Testable Design of Repeaterless Low Swing On-Chip Interconnect. CoRR abs/1511.06726 (2015)
Coauthor Index
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