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Journal Articles
- 2002
[j1]Mirko Benz, Uwe Hatnik, Klaus Feske, Jürgen Haufe:
Entwurfsunterstützung zur hardwarebasierten TCP/IP-Beschleunigung (Design Support for Hardware Based TCP/IP Accelerator). Informationstechnik Tech. Inform. 44(3): 153-159 (2002)
Conference and Workshop Papers
- 2002
- [c10]Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke:
Enhanced Reusability for SoC-Based HW/SW Co-Design. DSD 2002: 94-101 - [c9]Klaus Feske, Georg Heinrich, Berndt Fritzsche, Mark Langer:
SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications. FPL 2002: 1105-1109 - 2001
- [c8]Mirko Benz, Klaus Feske, Uwe Hatnik, Peter Schwarz:
TCP/IP Protocol Engine System Simulation. PROMS 2001: 155-164 - 1999
- [c7]Klaus Feske, Michael Scholz, Günther Döring, Denis Nareike:
Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler. FPL 1999: 243-252 - 1998
- [c6]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske:
Multi-Criterial State Assignment for Low Power FSM Design. EUROMICRO 1998: 10261-10268 - [c5]Klaus Feske, Steffen Rülke, Manfred Koegst:
FPGA based prototyping using a target driven FSM partitioning strategy. ICECS 1998: 89-92 - [c4]Manfred Koegst, Günter Franke, Klaus Feske, Steffen Rülke:
Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. MBMV 1998: 30-37 - 1997
- [c3]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske:
Low Power Design of FSMs by State Assignment and Disabling Self-Loops. EUROMICRO 1997: 323-330 - [c2]Klaus Feske, Sven Mulka, Manfred Koegst, Günter Elst:
Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs. FPL 1997: 235-244 - 1996
- [c1]Manfred Koegst, Klaus Feske, Günter Franke:
State assignment for FSM low power design. EURO-DAC 1996: 28-33
Coauthor Index
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