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Journal Articles
- 2019
[j4]Imad Benacer
, François-Raymond Boyer, Yvon Savaria:
A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. IEEE Access 7: 2231-2243 (2019)- [j3]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. IEEE Access 7: 130672-130684 (2019) - 2018
- [j2]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1939-1952 (2018) - 2016
- [j1]Imad Benacer, Zohir Dibi:
Extracting parameters of OFET before and after threshold voltage using genetic algorithms. Int. J. Autom. Comput. 13(4): 382-391 (2016)
Conference and Workshop Papers
- 2018
- [c6]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. ISCAS 2018: 1-5 - [c5]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. NEWCAS 2018: 229-233 - 2017
- [c4]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A high-speed traffic manager architecture for flow-based networking. NEWCAS 2017: 161-164 - 2016
- [c3]Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria:
A fast systolic priority queue architecture for a flow-based Traffic Manager. NEWCAS 2016: 1-4 - 2015
- [c2]Imad Benacer, Aicha Hamissi, Abdelhakim Khouas:
A novel stereovision algorithm for obstacles detection based on U-V-disparity approach. ISCAS 2015: 369-372 - [c1]Imad Benacer, Aicha Hamissi, Abdelhakim Khouas:
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach. ISCAS 2015: 2053-2056
Coauthor Index
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