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Zaid Al-Wardi

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Conference and Workshop Papers

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2018
[c5]
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. ISMVL 2018: 97-102
2017
[c4]
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Extensions to the Reversible Hardware Description Language SyReC. ISMVL 2017: 185-190
[c3]
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report. RC 2017: 102-108
2016
[c2]
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. ISMVL 2016: 31-36
2015
[c1]
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Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. RC 2015: 233-247

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